@inproceedings{Hyl2008,Author = {Hylla, Kai and Oetjens, Jan-Hendrik and Nebel, Wolfgang},Title = {Using SystemC for an extended MATLAB/simulink verification flow},Year = {2008},Pages = {221-226},Month = {09},Booktitle = {Specification, Verification and Design Languages, 2008. FDL 2008. Forum on},type = {inproceedings},note = {Functional verification is a major part of today's system design task. Several approaches are available for verification on a high abstraction level, where designs are often modeled using MATLAB/Simulink, as well as for RT-level verification. Different ap},Abstract = {Functional verification is a major part of today's system design task. Several approaches are available for verification on a high abstraction level, where designs are often modeled using MATLAB/Simulink, as well as for RT-level verification. Different approaches are a barrier to a unified verification flow. For simulation based RT-level verification, an extended test bench concept has been developed at Robert Bosch GmbH. This paper describes how this SystemC-based concept can be applied to Simulink models. The implementation of the resulting verification flow addresses the required synchronization of both simulation environments, as well as data type conversion. An example is used to evaluate the implementation and the whole verification flow. It is shown that using the extended verification flow saves a significant amount of time during development. Reusing test bench modules and test cases preserves consistency of the test bench. Verification is done automatically rather than by inspecting the waveform manually. The extended verification flow unifies system-level and RT-level verification, yielding a holistic verification flow.}}@COMMENT{Bibtex file generated on }