@inproceedings{Hyl2013,Author = {Hylla, Kai and Hartmann, Philipp A. and Helms, Domenik and Nebel, Wolfgang},Title = {Early Power \& Timing Estimation of Custom Hardware Blocks based on Automatically Generated Combinatorial Macros},Year = {2013},Month = {03},type = {inproceedings},note = {In this paper we present a technique for automatically estimating power and timing of full-custom hardware blocks, such as co-processors or hardware accelerators from algorithmic descriptions. The required characterisation is performed on a cycle-accurate},Abstract = {In this paper we present a technique for automatically estimating power and timing of full-custom hardware blocks, such as co-processors or hardware accelerators from algorithmic descriptions. The required characterisation is performed on a cycle-accurate functional description at register transfer level, which is obtained from a high-level synthesis. Characterisation results are used for generating a power and timing aware high-level simulation model. As an abstraction step, combinatorial macros are identified and characterised automatically. Characterisation takes place using RT-level power models, providing accurate estimates. Using the characterised macros, a power and timing annotated high-level simulation model is generated. This C++-based virtual prototype allows a fast, yet accurate estimation of the given design. Having a total error of about 3.6 % we achieve a speed-up of approximately 516x compared to an RT-level estimation, while giving cycle-accurate timing and power estimates.}}@COMMENT{Bibtex file generated on }