@inproceedings{Fakih:2013,Author = {Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim},Title = {Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking},Year = {2013},Month = {03},Publisher = {European Design and Automation Association},Series = {DATE '13},Address = {3001 Leuven, Belgium, Belgium},Booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2013},type = {inproceedings},note = {The timing predictability of embedded systems withhard real-time requirements is fundamental for guaranteeingtheir safe usage. With the emergence of multicore platformsthis task became very challenging. In this paper, a model-checking based approa},Abstract = {The timing predictability of embedded systems withhard real-time requirements is fundamental for guaranteeingtheir safe usage. With the emergence of multicore platformsthis task became very challenging. In this paper, a model-checking based approach will be described which allows us toguarantee timing bounds of multiple Synchronous Data FlowGraphs (SDFG) running on shared-bus multicore architectures.Our approach utilizes Timed Automata (TA) as a commonsemantic model to represent software components (SDF actors)and hardware components of the multicore platform. These TAare explored using the UPPAAL model-checker for providing thetiming guarantees. Our approach shows a significant precisionimprovement compared with the worst-case bounds estimatedbased on maximal delay for every bus access. Furthermore,scalability is examined to demonstrate analysis feasibility forsmall parallel systems.}}@COMMENT{Bibtex file generated on }