@inproceedings{Fakih:2013, Author = {Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim}, Title = {Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking}, Year = {2013}, Month = {03}, Publisher = {European Design and Automation Association}, Series = {DATE '13}, Address = {3001 Leuven, Belgium, Belgium}, Booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2013}, type = {inproceedings}, note = {The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task became very challenging. In this paper, a model- checking based approa}, Abstract = {The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task became very challenging. In this paper, a model- checking based approach will be described which allows us to guarantee timing bounds of multiple Synchronous Data Flow Graphs (SDFG) running on shared-bus multicore architectures. Our approach utilizes Timed Automata (TA) as a common semantic model to represent software components (SDF actors) and hardware components of the multicore platform. These TA are explored using the UPPAAL model-checker for providing the timing guarantees. Our approach shows a significant precision improvement compared with the worst-case bounds estimated based on maximal delay for every bus access. Furthermore, scalability is examined to demonstrate analysis feasibility for small parallel systems. } } @COMMENT{Bibtex file generated on }