@inproceedings{Gö2012,Author = {Görgen, Ralph and Oetjens, Jan-Hendrik and Nebel, Wolfgang},Title = {Automatic Integration of Hardware Descriptions into System-Level Models},Year = {2012},Month = {04},Isbn = {978-1-4244-9754-6},Booktitle = {Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems},Organization = {IEEE},type = {inproceedings},note = {In this paper, we present a flow for integrating hardware descriptions into Simulink simulations. It enables the automatic generation of a Simulink component out of a hardware component model given as RT level VHDL. The approach is based on two steps. T},Abstract = {In this paper, we present a flow for integrating hardware descriptions into Simulink simulations. It enables the automatic generation of a Simulink component out of a hardware component model given as RT level VHDL. The approach is based on two steps. The first step transforms the VHDL model to SystemC. In contrast to existing VHDL-to-SystemC transformation tools, the readability and onfigurability of the input model is preserved. In addition, our approach yields a more exact model, as a custom designed VHDL-like data-type system is employed. The second step generates a specific wrapper to allow the use of the component in a Simulink simulation. This transformation strategy will be evaluated with two industrial automotive electronics hardware designs. }}@COMMENT{Bibtex file generated on }