@conference{Pop2007,Author = {Poppen, Frank and Jährling, Alexander and Nebel, Wolfgang},Title = {Comparing Executable Specifications regarding Power at Algorithmic Level (ANSI-C/SystemC)},Year = {2007},Month = {03},Organization = {Cadence Design Systems, Inc.},type = {conference},note = {Nanometer scale design comes up with daunting challenges like signal integrity, design for yield and manufacturing or power dissipation. The latter is actually not a new challenge and EDA tools are available that allow for gate- and RT-level power estimat},Abstract = {Nanometer scale design comes up with daunting challenges like signal integrity, design for yield and manufacturing or power dissipation. The latter is actually not a new challenge and EDA tools are available that allow for gate- and RT-level power estimation and optimization. For maximum savings, it is mandatory to consider power in the earliest stages of a design flow, since only at highest levels of abstraction, e.g. algorithmic level, the complete design-space is open for exploration and optimization.}}@COMMENT{Bibtex file generated on }