@inproceedings{All2001,Author = {Allara, Alberto and Bombana, Massimo and Kruse, Lars and Nebel, Wolfgang and Schmidt, Eike and Stammermann, Ansgar},Title = {VHDL Behavioural Power Estimation for Telecom Devices},Year = {2001},Month = {01},Organization = {FDL '01, Forum on Design Languages. - New York, N.Y.: ACM},type = {inproceedings},note = {In this paper we propose and formalise a VHDL based design methodology integrating behavioural synthesis and power-driven design. In order to evaluate this approach, estimations of power consumption are analysed for alternative architectures of a telecom },Abstract = {In this paper we propose and formalise a VHDL based design methodology integrating behavioural synthesis and power-driven design. In order to evaluate this approach, estimations of power consumption are analysed for alternative architectures of a telecom design. Constrained behavioural and logic synthesis is then applied to generate the gate level netlist. A comparison with gate-level power evaluation is performed and commented. The flow is easily extendable to other application domains.}}@COMMENT{Bibtex file generated on }