@inproceedings{Sch1999,Author = {Schlör, R. and Allara, A. and Comai, S.},Title = {System Verification using User-Friendly Interfaces},Year = {1999},Pages = {167-172},Month = {01},Editor = {IEEE Computer Society Press},Publisher = {IEEE Computer Society Press},Booktitle = {Design, Automation and Test in Europe / User Forum},type = {inproceedings},note = {This paper reports on the use of a verification environment for VHDL based on automatic verification techniques 1. The paper focuses on two different aspects: (1) A graphical language and interface for the specification of properties called STDx (extended},Abstract = {This paper reports on the use of a verification environment for VHDL based on automatic verification techniques 1. The paper focuses on two different aspects: (1) A graphical language and interface for the specification of properties called STDx (extended Symbolic Timing Diagrams) is described and its application is illustrated. (2) A methodology for formal verification of system properties based on a combination of modelchecking and tautology-checking is suggested. - A first account of successful application of the techniques on a selected industrial design is given.}}@COMMENT{Bibtex file generated on }