@inproceedings{Bro1998,
Author = {Brockmeyer, U. and Wittich, G.},
Title = {Real-Time Verification of STATEMATE Designs -- Tool-Paper},

Year = {1998},
Pages = {537-541},
Month = {01},
Series = {Lecture Notes in Computer Science},
Booktitle = {Computer Aided Verification},
type = {inproceedings},
note = {This tool-paper presents a toolset for real-time verification of STATEMATE designs.
STATEMATE is a widely used design tool for embedded control applications. In our approach designs including all timing information are translated into untimed finite stat},
Abstract = {This tool-paper presents a toolset for real-time verification of STATEMATE designs.
STATEMATE is a widely used design tool for embedded control applications. In our approach designs including all timing information are translated into untimed finite state machines (FSMs) which are verified by symbolic model-checking. Real-time requirements are expressed by TCTL formulae interpreted over discrete time. A reduction from TCTL model-checking to CTL model-checking in order is implemented to use a CTL model-checker for the verification task. Some experimental results of the toolset are given.}
}
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