@article{Kim2020, Author = {Kim Grüttner and Philipp A. Hartmann and Tiemo Fandrey and Kai Hylla and Daniel Lorenz and Stefan Hauck-Stattelmann and Björn Sander and Oliver Bringmann and Wolfgang Nebel and Wolfgang Rosenstiel}, Title = {A Time Value Stream Based ESL Timing \& Power Estimation and Simulation Framework for Heterogeneous MPSoCs}, Journal = {International Journal of Parallel Programming}, Year = {2020}, type = {article}, Abstract = {Consideration of an embedded system's timing behavior and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. In this article we present an ESL framework for timing and power aware virtual system prototyping of heterogeneous MPSoCs consisting of software, custom hardware and 3rd party IP components. Our proposed ESL framework supports the integration of a broad range of system-level timing and power models into virtual platforms. Power and timing models can either be generated from a functional C/C++ description (white-box) or include state-machine based power models into existing functional and timed virtual platform (black-box) components. Our timed value stream based power model supports run-time analysis of different platform power management strategies with configurable temporal abstraction, supporting simulation speed and accuracy trade-offs. This work evaluates the application of timing and power back-annotation by applying white-box and black-box (power state machines) approaches in SystemC based virtual platforms, building on the concept of timed value streams. The evaluation is performed on two case studies: An MP3 decoder SoC and an FPGA based many-core architecture with power management capabilities. In the two case studies a comparison of the power aware virtual platform against a power-aware ISS, a gate-level simulation and measurements is performed.} } @COMMENT{Bibtex file generated on }