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Wissenschaftlicher Mitarbeiter
Verkehr / E/E Architektur Analyse & Design
Designmethodik HW-/SW-Systeme
O111
+49 441 9722-296
OFFIS
raphael.weber [ A T ]
offis.de
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture
Latency Optimization for a Reconfigurable, Self-Timed and Bit-Serial Architecture
Low Level Space Optimization of an AES Implementation for a Bit Serial Fully Pipelined Architecture
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture
Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture