Tagungsbeitrag
Schmidt, Eike; Huijbrechts, E.; Seelen, E.; Nieuweboer, W.; Kruse, Lars; von Cölln (Jochens), Gerd; Nebel, Wolfgang
This paper addresses the problem of modeling the power consumption of on-chip ROMs for gate-level and RT-level power estimations. A route to memory power model development is presented that is also applicable to other memory architec-tures. The model proposed operates within an error margin of less than 5%.
1998
PATMOS 1998, Lyngby / Denmark