The primary objective of COMPLEX is to develop an innovative, highly efficient and productive design methodology and a holistic framework for iteratively exploring the design space of embedded hardware/software (HW/SW) systems.
COMPLEX consortium develops a new design environment for platform-based design-space exploration offering developers of next-generation mobile embedded systems a highly efficient design methodology and tool chain. The integrated environment allows iterative exploration and refinement of advanced applications to meet market requirements. The design technology in particular enables fast simulation and explores the use of different implementations at Electronic System Level (ESL) with up to bus-cycle accuracy at the earliest instant in the design cycle. The main objectives are:
01.12.2009
30.11.2012
The COMPLEX framework is a design flow with performance and power aware virtual prototyping of an embedded HW/SW system. Several well established ESL synthesis and analysis tools from vendors such as CoWare, ChipVision, EDALab, and Magillem will be augmented and combined into the seamless COMPLEX design flow.
For co-development the COMPLEX framework follows a new approach using a unified internal representation of the HW and SW, called block annotated C++ (BAC++). It is generated by SW cross-compilers and HW behavioural synthesis tools. In the COMPLEX framework, the generated BAC++ code is integrated into a SystemC™/TLM2 virtual platform model, enabling fast system simulation.
The hardware/software co-exploration considers both the architecture design space and the application space to assess trade-offs when designing next-generation embedded systems. The co-exploration is multi-objectively assessing the design quality and optimizing the system platform with respect to performance, power, reliability metrics, etc. The optimization benefits from run-time mode adaption techniques, such as dynamic power management or application adaption to evolving workloads, can be maximised and reported to successive synthesis steps using standardized output formats.
The framework combines several standards for system modelling and integration: Possible design entry is either in C++/SystemC or a MARTE/UML model, offering seamless integration into a model-driven design approach.